A low-complexity implementation of a transmitter concept for transceivers in mobile radio systems is provided by transmitters having a modulator which operates on the known principle of single-point modulation. A PLL (phase locked loop) circuit is employed in this case as a frequency synthesizer and is used for phase or frequency modulation of a radio-frequency signal.
In a single-point modulator, the digital modulation data is usually injected into the feedback path of the PLL circuit. The latter contains a programmable frequency divider which is driven by a digital modulation signal. The digital modulation signal determines that number by whose reciprocal the instantaneous frequency of the input signal for the frequency divider is multiplied.
The bandwidth of the PLL circuit must satisfy two competing conditions. On the one hand, the bandwidth must be as narrow as possible in order to be able to comply with predetermined noise requirements of a spectral transmit mask. On the other hand, transmission of the modulated data requires a wide bandwidth.
The article “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation” by Michael H. Perrott, Theodore L. Tewksbury III and Charles G. Sodini, which appeared in the IEEE Journal of Solid-State Circuits, Volume 32, Issue 12, 1997, pages 2048-2060, discloses a single-point modulator which is used in an attempt to satisfy the abovementioned conditions. In this single-point modulator, the noise requirements mean that the bandwidth of the PLL control loop is designed to be considerably narrower than would actually be required for transmitting the modulated data. In order to compensate for the narrow bandwidth, the digital modulation data is first of all prefiltered by means of a digital filter and is then supplied to a sigma-delta modulator before being fed into the frequency divider in the PLL circuit. The disadvantage of a single-point modulator of this type is the requisite matching accuracy between the digital filter for prefiltering the digital modulation data and the analogue loop filter which is usually provided in a PLL circuit.
Two-point modulation provides another known option for compensating for the reduced bandwidth of a PLL control loop. A two-point modulator is based on a single-point modulator. In addition, in a two-point modulator, an analogue modulation signal is injected into a summation point which is situated in the forward path of the PLL circuit and is preferably connected upstream of the voltage-controlled oscillator. The analogue modulation fed in at the summation point has a high-pass filtering effect on the output of the PLL circuit on account of the closed control loop. In contrast, the programmable frequency divider into which the digital modulation signal is fed represents a point in the PLL circuit at which a low-pass transmission response for injecting modulation results. The digital and analogue modulation signals are superimposed at the output of the PLL circuit, thus resulting in the PLL circuit having a frequency-independent transmission response. A two-point modulator of this type is described, for example, in German laid-open specification DE 199 29 167 A1. The disadvantage of a two-point modulator is that its circuitry is more complex than that of a single-point modulator.